BANDWIDTH OPTIMIZATION TO ACHIEVE MINIMUM PHASE NOISE IN FREQUENCY SYNTHESIZERS

This paper analyzes the phase noise of the single loop second-order frequency
fractional-N synthesizer. The aim of this paper is the reduction of the output phase noise in the
application of commercial and military subsystems as well as general local oscillators. The
mathematical model of PLL based frequency synthesizer is analyzed to develop the minimum
phase noise in the specific frequency range. An exact closed form relationship between bandwidth
and output phase noise of the frequency synthesizer as well as the bandwidth-phase noise diagram
is extracted by using this closed form relationship. From the analysis and simulation results, we
observe that the system has minimum phase noise at a particular closed-loop bandwidth. To
validate simulation results, the synthesizer is implemented on the low loss professional printed
circuit board (PCB). Measurement setup is scheduled on spectrum analyzer 8562A in the span of
5MHz and 10MHz. These measurements show excellent results in output spectrum of the
frequency synthesizer.